`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    20:48:58 01/08/2014 
// Design Name: 
// Module Name:    control_and_clocking 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module control_and_clocking(
	input clk,
	input pseudo_switch,
	input face_switch,
	input [7:0] pixel_data_r,
	input [7:0] pixel_data_g,
	input [7:0] pixel_data_b,
	input [7:0] pseudo_data_r,
	input [7:0] pseudo_data_g,
	input [7:0] pseudo_data_b,
	input [7:0] face_data,	
	output reg [7:0] cc_output_data_r,
	output reg [7:0] cc_output_data_g,
	output reg [7:0] cc_output_data_b
);

wire [7:0] output_r;
wire [7:0] output_g;
wire [7:0] output_b;

switching_module switcher (
		.pseudo_switch(pseudo_switch), 
		.pixel_data_r(pixel_data_r), 
		.pixel_data_g(pixel_data_g), 
		.pixel_data_b(pixel_data_b), 
		.pseudo_data_r(pseudo_data_r), 
		.pseudo_data_g(pseudo_data_g), 
		.pseudo_data_b(pseudo_data_b), 
		.face_switch(face_switch), 
		.face_data(face_data), 
		.clk(clk),
		.output_data_r(output_r), 
		.output_data_g(output_g), 
		.output_data_b(output_b)
	);

always @(posedge clk)
begin
	cc_output_data_r <= output_r;
	cc_output_data_g <= output_g;
	cc_output_data_b <= output_b;

end

endmodule
